Interface AD7823

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Summary

This VHDL macro is intended for interface (say) PicoBlaze with the 8-bit ADC AD7823 from Analog Devices or compatible ones. Such device is included in Digilent AIO1 peripheral board sold by Digilent.

VHDL Macro

xc3s400-4ft256 utilization
Element	Used
Slices	22
Flip-Flops	28
LUTs	41
Bonded IOBs	16
Global CLKs	2
Max Freq.	200.942MHz

component ad7823
  port (
    reset    : in     std_logic;
    clk      : in     std_logic;
    clk10MHz : in     std_logic;
    start    : in     std_logic;
    eoc      : out    std_logic;
    do       : buffer std_logic_vector(7 downto 0);
    di       : in     std_logic;        -- to ad7823
    sclk     : out    std_logic;        -- to ad7823
    convst   : out    std_logic);       -- to ad7823
end component;

AD7823 pinout

The AD7823 is an 1-channel 8-bit DAC with a synchronous serial interface. It seems that the most appropriated solution to interface this device is to use a FSM and a shift register.

The circuit waits the start signal to initiate the conversion and puts the acquired 8-bit sample after 5us (250 system clock cycles @50MHz). The maximum ADC sample rate is 200kSPS, enough for audio applications.

Ports and Usage

The macro has the following ports:

Port	DIR	Type	Description
reset	Input	signal	Asynchronous reset
clk	Input	signal	Clock signal (> 30MHz)
clk10MHz	Input	signal	Slow clk for internal macro use (measure time)
start	Input	signal	Start ADC conversion
eoc	Output	signal	End Of Conversion, it's a "ready" signal that notifies that the conversion has ended and it is possible to order a new conversion
do	Output	8-bit bus	The 8-bit sample read from AD7823
di	Input	signal	Serial data input from AD7823
sclk	Output	signal	Control signal for AD7823 (clock signal)
convst	Output	signal	Control signal for AD7823 (initiates the ad7823)

After power up the circuits, wait at least 6us. Then assert start and wait for eoc to go 1 (only for one clk cycle, use it as a interrupt signal if you want), the acquired 8-bit sample will be present at do port. Repeat as many times as you want.

Block Diagram And Control State Machine

The figure depicted below shows the RTL block diagram of the circuit. All sequential blocks share the same asynchronous reset and clock signals. The control finite state machine (FSM) has 11 states, there are 7 control signals for datapath.

Datapath

Control

The FSM has the following graph, state after reset is e0, the control signals in each state are shown in the table. The signals printed in green are registered because random effects on this signals could cause a malfunctioning of entire system (AD7823 expects inputs free of spurious transitions)

Control signals for datapath
State	ctlrs	ctr_ce	sh_ce	eoc	sclk	convst
e0	1	0	0	0	0	1
e1	0	0	0	0	0	0
e2	1	0	0	0	0	0
e3	0	0	0	0	0	1
e4	0	0	0	0	0	0
e5	1	0	0	0	0	1
e6	0	0	0	0	1	1
e7	0	1	1	0	1	1
e8	1	0	0	1	0	1
e9	0	0	0	0	0	1
e10	1	0	0	1	0	1

Download

ad7823.vhd AD7823 interface macro.
ad7823_test.vhd Test Bench
[es] AD7823_LEEME.txt

References

AD7823 Datasheet