Interface AD7303

From JavierValcarce.Es

VHDL Macro

component ad7303
  port (
    reset   : in  std_logic;
    clk     : in  std_logic;  
    wr      : in  std_logic;
    XL_wr   : in  std_logic;
    XR_wr   : in  std_logic;
    XL      : in  std_logic_vector(7 downto 0);
    XR      : in  std_logic_vector(7 downto 0);
    rdy     : out std_logic;
    int_rdy : out std_logic;
    sclk    : out std_logic;
    din     : out std_logic;
    sync    : out std_logic);
end component;

AD7303 pinout

The AD7303 is an 2-channel 8-bit DAC with a SPI interface. Rather than use a complete, general SPI master transceiver, I developed an specific (ad hoc) interface logic which is extremely simple and easy to use from PicoBlaze or some system else.

The interface moves two 8-bit samples in 68 system clock cycles so the maximum DAC data rate @50MHz is kHz for each channel. The predefined configuration for AD7303^[1] is

• the two DAC channels enabled
• collect data from the shift register instead from input register
• set the internal reference (V_dd / 2)

Ports and Usage

The macro has the following ports:

Put data samples on XL and XR ports and assert XL_wr and XR_wr until the next clk rising edge, then assert wr signal until the clk rising edge. At this moment rdy goes 0, the sample will be transferred to DAC in 68 clock (clk) cycles. Wait rdy signal to be 1 again, this notifies you that the transmission has finished. See the cronogram below.

Block Diagram And Control State Machine

The figure depicted below shows the RTL block diagram of the circuit. All sequential blocks share the same asyncronous reset and clock signals. The control finite state machine (FSM) has 9 states, there are 6 control signals for datapath. The 4-bits up counter serves to greatly simply the FSM's graph.

Datapath

Control

The FSM has the following graph, state after reset is e0, the control signals in each state are shown in the table. The value '-' means "no matter", this is very convenient because it relieves the constraints over the job that has to be done by the synthesizer, the synthesized circuits are simpler.

Simulation

Cronogram in ModelSim. Transmission of 2 8-bit samples in 68 clk cycles:

(todo)

Download

• ad7303.vhd AD7303 interface macro. Thanks to Faisal Abu-Nimeh, who fixed an error in SPI transmision.
• ad7303_test.vhd Test Bench for AD7303 interface macro.
• utils.vhd Utils package.

References

• AD7303 Datasheet